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Curriculum Vitae

Personal Data
Name: Assoc.Prof.Piya Kovintavewat, Ph.D.
Nationality: Thai
Email Addresses: piya@npru.ac.th


Addresses:
  • Data Storage Technology Research Unit 
    Faculty of Science and Technology
    Nakhon Pathom Rajabhat University
    85 Moo 3, Malaiman rd.
    Mueang District, Nakhon Pathom 73000, Thailand
Qualifications:
Jan. '00 - Dec. '05: Georgia Institute of Technology, Atlanta, USA
 
  • Ph.D. in Electrical Engineering (Telecommunication)
Sept. '97 - Nov. '98:  Chalmers University of Technology, Göteborg, Sweden
 
  • M.Sc. in Digital Communication Systems and Technology
May '90 - Mar. '94:  Thammasat University, Bangkok, Thailand
 
  • B.Eng. in Telecommunication (Hons.)

Award Received:  
  • Royal Thai Government Scholarship (2000 - 2004).
  • Graduate Research Assistantship, Georgia Institute of Technology, USA (2001 - 2004).
  • STINT Scholarship, Chalmers University of Technology, Sweden (1997-1998).

Work Experiences: 
 
Sept’09 – present:  Associate Professor, Nakhon Pathom Rajabhat University, Thailand
Jun’06 – Sept’09: Assistant Professor, Nakhon Pathom Rajabhat University, Thailand
Dec’04 – Jun’06: Lecturer, Nakhon Pathom Rajabhat University, Nakhon Pathom, Thailand
Jan.'01 - Dec. '05:  Graduate Research Assistant, Georgia Institute of Technology, Atlanta, USA
 
  • Determine an efficient algorithm for timing recovery system as applied to digital data storage.
  • Design a powerful detector used for magnetic recording systems.
May '04 - Aug. '04:  Technical Intern, Seagate Technology, Pittsburgh, USA
 
  • Reduced the complexity of per-survivor iterative timing recovery with negligible performance loss.
  • Incorporated a pattern-dependent noise-predictive technique in per-survivor iterative timing recovery to cope with the media noise dominated channel.
May '02 - Aug. '02:  Technical Intern, Seagate Technology, Pittsburgh, USA
 
  • Investigated and analyzed the performance of  the oversampled timing recovery operating at twice the symbol-rate sampling.
  • Designed and analyzed a new timing recovery architecture called "per-survivor processing (PSP) -based timing recovery."
May '01 - Aug. '01:  Technical Intern, Seagate Technology, Pittsburgh, USA
 
  • Designed a GPR target and an interpolated timing recovery (ITR) system for perpendicular recording.
  • Evaluated and tested their performance with simulated perpendicular signals.
Dec. '98 - Dec. '99:  Research Assistant, Network Technology LabNECTEC, Thailand
 
Apr. '94 - Aug. '97:  Senior Engineer, Area Coordination and Improvement Planning Division, Thai Telephone and Telecommunication Public Company Limited (TT&T), Thailand
 
  • Installed and managed a line test system nationwide.
  • Generated and distributed the operating manuals regarding how to deliver customer satisfaction.
  • Supported area Telecommunication Business Activities.
Work Achievements:
  • Attended a training course about Alcatel switching system at Alcatel Training Center in France for 2 months.
  • Served as a coordinator on telecommunication services in "World Tech'95 Thailand" (World Exposition an Agro-Industrial Technology) and 18th SEA GAMES.
Technical Skills:
  • Programming Laguages:

  • C, C++, Java, Pascal, MATLAB, HTML, LaTeX

     

  • Operating Systems:

  • Unix, MS-DOS, Window95/98/NT/2000/XP
  • Software Packages:

  • Excel, Winword, Powerpoint, Framemaker, Photoshop
Technical Reports: Languages: Thai, English, and French (Beginner)

Reference: Upon requested