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Professor Piya Kovintavewat, Ph.D. 

Lecturer/Researcher
Electrical Engineering Program 
Faculty of Science and Technology

Nakhon Pathom Rajabhat University
85 Moo 3, Malaiman Rd.
Mueang District, Nakhon Pathom 73000, Thailand
Phone: (+663) 426-1024 Ext. 1827
Fax: (+663) 426-1065
Email: piya@npru.ac.thpkovintavewat@yahoo.com

Dr. Piya Kovintavewat received the B.Eng. summa cum laude from Thammasat University, Thailand (1994), the M.S. degree from Chalmers University of Technology, Sweden (1998), and the Ph.D. degree from Georgia Institute of Technology (2004), all in Electrical Engineering. For more, see my resume. His thesis work titled "Timing Recovery Based on Per-Survivor Processing" was awarded second prize for new Ph.D. thesis in the field of information technology by the National Research Council of Thailand in 2005.

He is currently a Professor in Electrical Engineering program, Faculty of Science and Technology, Nakhon Pathom Rajabhat University (NPRU), Nakhon Pathom, ThailandHis main research interests include coding and signal processing as applied to digital data storage systems.

Prior to working at NPRU, he worked as an engineer at Thai Telephone and Telecommunication company (1994-1997), and as a research assistant at National Electronics and Computer Technology Center (1999), both in Thailand. He also had work experiences with Seagate Technology, Pennsyl       vania, USA (summers 2001, 2002, and 2004).

Work Experiences

Feb’19 – Present       Professor
                              Nakhon Pathom Rajabhat University, Thailand

Sept’09 – Feb'19       Associate Professor
                              Nakhon Pathom Rajabhat University, Thailand

Jun’06 – Sept’09       Assistant Professor
                                
Nakhon Pathom Rajabhat University, Thailand

Dec’04 – Jun’06        Lecturer, Nakhon Pathom Rajabhat University, Thailand

Jan’01 – Dec’04        Graduate Research Assistant, Georgia Tech, USA

  • Designed and investigated efficient timing recovery schemes, as applied to digital data storage systems

May’04 – Aug’04         Technical Intern, Seagate Technology, Pittsburgh, USA

  • Developed reduced-complexity per-survivor iterative timing recovery for coded partial response channels
  • Incorporated a pattern-dependent noise-predictive technique in the proposed timing recovery scheme to handle media noise dominated channels

May’02 – Aug’02         Technical Intern, Seagate Technology, Pittsburgh, USA

  • Investigated and analyzed the performance of oversampled timing recovery operating at twice the symbol-rate sampling
  • Developed new timing recovery schemes based on per-survivor processing technique

May’01 – Aug’01         Technical Intern, Seagate Technology, Pittsburgh, USA

  • Designed a GPR target and an interpolated timing recovery (ITR) system for perpendicular recording
  • Evaluated and tested the performance of the GPR target and ITR

Dec'98 – Dec’99          Research Assistant, Network Technology Laboratory
                                     National Electronics and Computer Technology Center
                                     (NECTEC), Thailand

  • Managed two projects, namely, Public-Key Infrastructure and Thailand Smart Card Standard projects

Apr’94 – Aug’97          Senior Engineer, Area Coordination Division
                                    Thai Telephone and Telecommunication (Pcl.), Thailand

  • Responsible for installing and managing line test systems, analyzing the fault statistics, and supporting area telecommunication business activities
 


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